Interviewing IBM's Christian Zoellin and Christian Jacobi

IBM unveiled a dual-ISA processor that runs both z/Architecture and ARM code, using a shared decode pipeline with separate decoders for the 16- to 48-bit z instructions and 32-bit ARM instructions. The load-store unit handles endian conversion and unaligned accesses in hardware, while all memory operations remain strongly ordered, providing automatic TSO support with only modest additional transistor cost.