Samsung's Processing-in-Memory (PIM)

Samsung’s LPDDR5X-PIM chips integrate a MAC block in each of 16 banks, giving 614 GB/s internal bandwidth versus a 76.8 GB/s external limit. Each block executes four INT8 or FP8 MACs per clock (eight per DDR cycle), delivering 2.4 TOPS per chip and up to 9.6 INT8 TOPS with eight chips. The design uses standard LPDDR5X commands and dedicated row addresses to switch between single-bank and multi-bank modes, routing reads/writes to PIM registers so software can load weights into DRAM and then enable multi-bank mode for accelerated inference.