Xcena and Samsung's Near Memory Compute CXL Device

XCENA and Samsung’s MX1 device adds up to 2 TB of DDR5 memory via a PCIe 6/CXL 3.2 ×8 link, delivering 128 GB/s total bandwidth and eight downstream PCIe 6 lanes for SSDs that can be cached in DRAM. The board’s 4 nm-fabricated processor hosts 3,072 low-power RISC-V cores (1.1 GHz, ~13 mW each) organized into 24 subsystems, enabling 24 parallel jobs with a GPU-like cache hierarchy and an OpenCL-style programming model.